1. Technical Field:
The present invention relates to a semiconductor device for use in, for example, ultra-high density integrated circuits.
2. Background Art:
In recent years, the degree of integration of Si grows increasingly with large strides to cause earnest research development to make fine sizes of constituent elements ranging from 1 .mu.m to 0.5 .mu.m or less. Along with such developments of elements made in fine sizes and LSIs made ultra-high in integration, metal wires for use in signal transmission in those LSIs are also increasingly required to be made fine and with high density.
As to metal wire materials for those LSIs, alloys based upon Al such as Al-Si, Al-Cu-Si and the like are widely employed at present. Those materials, however, suffer from diverse problems when wires of those materials are made fine and of high density. FIG. 2 (a) and 2 (b) here illustrate the results of observations of surfaces of Al-Si, which are formed by DC magnetron sputtering widely used conventionally, with use of a Nomarsky differential interference microscope. Films with thickness of about 1 .mu.m are formed by heating a substrate to 250.degree. C. FIG. 2 (a) shows the surface of Al-Si just after the film formation by the DC magnetron sputtering, and FIG. 2 (b) shows the surface of the same after annealing for 30 minutes in forming gas at 400.degree. C. As evidenced by photographs in the figures, the heat treatment causes uneveness on the surfaces of the Al film. These unevennesses are called hillock, the sizes of which range from 0.5 to 1 .mu.m or more. Such hillocks greatly reduce the yield of LSIs for the reason which will be described with reference to FIG. 3.
FIG. 3 (a) is a schematic cross sectional view illustrating a two-layer wiring structure. Numerals 301, 302, and 303 designate insulating films of for example SiO.sub.2. Numerals 304 and 304' designate the first-layer Al-Si wiring, and 305 designates the second-layer one, both the wirings being insulated by an interlayer insulating film 302. In addition, the numeral 306 designates a hole made through the interlayer insulating film 302 for electrically connecting the first layer wiring 304' with the second one 305, which hole is called a through hole or via here, and the numeral 307 designates a hillock produced on the upper surface of the first layer wiring 304 where the thickness of the interlayer insulating film 302 is made thinner. This may cause reduced dielectric strength at this portion as compared with other portions where no hillock is produced.
Now, on the assumption that the thickness of the interlayer film 302 at the portions with no hillock is T, the hight of the hillock is H, and the strength of an electric field, by which the interlayer film 302 is rendered to dielectric breakdown, is E.sub.b, dielectric breakdown voltage V.sub.b ' between the wiring 304 and 305 is expressed by EQU V.sub.b '=E.sub.b (T-H) (1)
while, dielectric breakdown without the existence of a hillock is expressed by EQU V.sub.b =E.sub.b T (2)
From (1) and (2), EQU V.sub.b '/V.sub.b =1-H/T (3)
holds. This indicates that the ratio V.sub.b '/V.sub.b becomes very small as the height H of the hillock gets nearer to the thickness T of the interlayer insulating film.
FIG. 4 (a) shows experimental data illustrating the distribution of the breakdown voltages of the interlayer insulating film, and FIG. 4 (b) is a cross sectional view of the measured sample. After the first layer Al-Si film 403 is formed on a silicon substrate 401 via an about 1 .mu.m -thick thermal oxidation film 402, a plasma SiO.sub.2 film 404 is deposited by about 1.6 .mu.m over the whole surface thereof. Thereafter, the whole surface is spin-coated by about 1 .mu.m with a resist and cured by baking, and then subjected to anisotropic etching on condition of the resist and SiO.sub.2 (404) being etched at the same speed, for the purpose of making the surface flat. Thereupon, the thickness of the plasma SiO.sub.2 film 404 at the flattened portion is made 1.2 .mu.m. Thereafter, a second Al-Si film 405 is deposited and patterned into a 200 .mu.m square. Moreover, the first layer Al-Si film 403 is a solid film with no patterning. The dielectric breakdown voltage is measured by applying DC voltage to the upper and lower metal films 405, 403 to thereby determined the voltage of the plasma SiO.sub.2 film 404 where it is conducted by its breakdown.
Referring here to FIG. 4(a), the breakdown valtage varies widely from 100V to 700V owing to the distributed heights of the hillocks. The highest hillock falling within the range of a 150 .mu.m square sample is considered to specify the breakdown voltage. The highest breakdown voltage of 700V is now assumed to be one specified when the heights of the hillocks are not so high as to influence the breakdown voltage. That is, this is assumed to be breakdown voltage V.sub.b without the presence of a hillock. Against this, the lowest breakdown voltage of 100V corresponds to the breakdown voltage V.sub.b ' at the location of the highest hillock, and EQU 100/700=1-H/T
holds from the equation (3).
On the assumption of T=1.2 .mu.m, H become about 1 .mu.m. From this, the highest hillock is found to be about 1 .mu.m.
Hereupon, the first layer Al-Si film of the sample shown in FIG. 4 (b) estimated just in the above is one formed by raising the wafer temperature upon its deposition to 250.degree. C. and subjecting it to DC-magnetron sputtering. That includes no heat treatment beyond 250.degree. C. after the deposition. That is, the surface is in the same state as the surface shown in FIG. 2(a) with reduced production of the hillocks compared with the sample subjected to the heat treatment at 400.degree. C. (FIG. 2 (b)). The present sample however still suffers from the reduction of the breakdown voltage. So, a number of samples similar to the one shown in FIG. 4 (b) are prepared by rendering the samples, after depositing the first layer Al-Si film 403, to heat treatment at 400.degree. C., and are then subjected to measurements of the breakdown voltage. As a result, almost all the samples exhibit the breakdown voltage of OV.
As described above, the multi-layer wiring construction reduces the dielectric breakdown voltage of the interlayer insulating film owing to the existence of hillocks. To solve this problem, there is a method of thickening the interlayer insulating film 302. However, this causees film stress to be increased whereby cracks are produced in the film and which result in bad insulation thereof. In addition, such stress enhances a stress migration effect in the metal wiring to thereby shorten the life of the wiring. Thereupon, even if the stress can be sufficiently reduced, a thick film is obliged to have its through hole 306 made deeper to thereby result in difficult fine processing as well as to break the metal wiring at its through hole. This method therefore has many problems.
As described above, the Al-Si film made in the DC magnetron sputtering method suffers from the production of hillocks followed by some problems. Those hillocks are likewise produced in an Al-Cu-Si film, a pure Al film, and the like. There is found no Al-based thin film without such hillocks at present whichever methods such as a RF sputtering method, high-vacuum deposition, CVD, etc, may be employed for its formation. The mechanism of hillock production has not yet been revealed until now and may considered to be due to migration of Al atoms along intercrystalline field. To prevent such migration, some methods have been devised, wherein a high melting point metal such as Ti is introduced into the Al film to thereby suppress the diffusion of Al atoms in the intercrystalline field. These methods are however not only imperfect but also unfavorable to future realization of ultra-high speed LSIs. They are thus not adoptable. The reason is that the key to put high-speed LSIs into practice is to reduce wiring resistance, and although pure metal reduces phonon scattering by lowering its temperature followed by the lowering of its resistance almost in proportion to absolute temperature, wirings made of materials such as alloys and materials involving any impurity permit impurity scattering to dominate at low temperature and thus hinder the effect of the resistance reduction manifested owing to the low temperature.
As the above description shows, the present status of arts can not achieve the wirings without hillocks. That is, there is demonstrated at present very unsatisfactory wiring technology for submicron range ultra-LSIs excellent both in reliability and yield thereof.